Semiconductor wafers are typically fabricated with multiple copies of a desired integrated circuit design that will later be separated and made into individual chips. A common technique for forming the circuitry on a semiconductor wafer is photolithography. Part of the photolithography process requires that a special camera focus on the wafer to project an image of the circuit on the wafer. The ability of the camera to focus on the surface of the wafer is often adversely affected by inconsistencies or unevenness in the wafer surface. This sensitivity is accentuated with the current drive for smaller, more highly integrated circuit designs which cannot tolerate certain nonuniformities within a particular die or between a plurality of dies on a wafer. Because semiconductor circuit on wafers are commonly constructed in layers, where a portion of a circuit is created on a first layer and conductive vias connect it to a portion of the circuit on the next layer, each layer can add or create topography on the wafer that must be smoothed out before generating the next layer. Chemical mechanical planarization (Oxide-CMP) techniques are used to planarize and polish each layer of a wafer. CMP (Metal-CMP) is also widely used to shape within-die metal plugs and wires, removing excess metal from the wafer surface and only leaving metal within the desired plugs and trenches on the wafer. Available CMP systems, commonly called wafer polishers, often use a rotating wafer holder that brings the wafer into contact with, for the most conventional rotary CMP machines, a polishing pad rotating in the plane of the wafer surface to be planarized. A chemical polishing agent or slurry containing microabrasives and surface modifying chemicals is applied to the polishing pad to polish the wafer. The wafer holder then presses the wafer against the rotating polishing pad and is rotated to polish and planarize the wafer. Some available wafer polishers use orbital motion, or a linear belt rather than a rotating surface to carry the polishing pad. In all instances, the surface of the wafer is often completely covered by, and in contact with, the polishing pad to simultaneously polish the entire surface.
One drawback of polishing the entire surface simultaneously is that the various circuits on the wafer may have a different response to the CMP process, even if the wafer begins the CMP process perfectly flat. This may be due to the different types of materials deposited on parts of the wafer or the density of materials on a certain portion of the wafer. Simultaneous polishing of the entire surface also often clears some spots of the wafer faster than others because of the different material properties. The uneven clearance results in over polishing of certain areas of the wafer. Additionally, various material processes used in formation of wafers provide specific challenges to providing a uniform CMP polish to a wafer. Certain processes, such as the copper dual damascene process, can be particularly sensitive to the overpolishing that may occur in polishers that simultaneously polish the entire surface of a wafer.
The trend to process larger diameter wafers has introduced an additional level of difficulty to the CMP process by requiring uniformity over a greater surface area. Using traditional CMP techniques, in which the entire surface of a wafer is covered by the polishing pad, larger diameter wafers significantly increase loading distribution requirements on the polishing pad or wafer in order to avoid pressure variations on the surface of the wafer as achieved with smaller diameter wafers. Fixed-abrasive polishing pads are sometimes desirable to perform some particular phases of the polishing process, however fixed-abrasive polishing pads can require even greater pressures than traditional non-abrasive pads to take full advantage of the planarization capabilities of the fixed-abrasive material.
Accordingly, there is a need for a method and system of performing chemical mechanical planarization and polishing that addresses these issues.